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NXP Semiconductors /MIMXRT1011 /SystemControl /ID_PFR0

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Interpret as ID_PFR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (STATE0_0)STATE00 (STATE1_0)STATE10STATE20STATE3

STATE0=STATE0_0, STATE1=STATE1_0

Description

Processor Feature Register 0

Fields

STATE0

ARM instruction set support

0 (STATE0_0): ARMv7-M unused

1 (STATE0_1): ARMv7-M unused

2 (STATE0_2): ARMv7-M unused

3 (STATE0_3): Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions.
STATE1

Thumb instruction set support

0 (STATE1_0): The processor does not support the ARM instruction set.

1 (STATE1_1): ARMv7-M unused
STATE2

ARMv7-M unused
STATE3

ARMv7-M unused

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data